Default Value In Verilog

Discussing Verilog and PLI

In VHDL I learned to set defaults in a combinatorial process so as not to infer
latches.  In verilog this would involve having a non blocking assigment such as
always @(something)
   if( something)
I looked at the LRM.  It says in section 5.4.
So it seems like It might be ok from a simulation point of view.

But ... Is this an acceptable coding style for verilog synthesis?

PS: I also tend to do things like this...
always @(posedge clk)
   case something
      0: x<=1;
      1: y<=1;

can save typing if there are many cases.                                            
Fine.  Do it.  Synthesis is committed to doing The Right Thing (tm),
i.e. to building hardware that mimics simulation behaviour - or,
if it can't do so, to let you know in no uncertain terms.

By the way, you should probably modify your coding style to 
use blocking assignment IF AND ONLY IF you are writing a 
combinational block:

always @(a or b or selector) begin
  y = a;
  if (selector)
    y = b;

always @(posedge clock) begin
  y <= a;
  if (selector)
    y <= b;

Always use blocking assignment in combinational blocks;
always use nonblocking assignment when assigning to 
any flip-flop whose output will go outside your 
clocked always block - i.e. anything that you're
using like a VHDL signal, to go from one process to
another.  Google for "cummings nonblocking verilog"
to find Cliff Cummings's classic paper on this;
trawl through this NG and elsewhere to find a 
perhaps slightly more interesting story relating to
assignments to local registers in a clocked always