Steve Steve 10 Jan 2005 In VHDL I learned to set defaults in a combinatorial process so as not to infer latches. In verilog this would involve having a non blocking assigment such as always @(something) x<=0; if( something) x<=1; end I looked at the LRM. It says in section 5.4. So it seems like It might be ok from a simulation point of view. But ... Is this an acceptable coding style for verilog synthesis? PS: I also tend to do things like this... always @(posedge clk) x<=0; y<=0; case something 0: x<=1; 1: y<=1; endcase end can save typing if there are many cases.